The present invention relates to an access controller and an access method and, more particularly, to an access controller and an access method for controlling access from a CPU (Central Processing Unit) to a memory.
FIG. 5 is a block diagram partly illustrating a structure of a prior art information processor. This Figure shows a structure associated with access from a CPU 160 or first and second processing circuits 500 and 510 to a DRAM (Dynamic Random Access Memory) 120.
The information processor as shown in FIG. 5 comprises the CPU 160, an access port 140, the DRAM 120, a bus arbiter 130, and the first and second processing circuits 500 and 510. Assume that the access port 140, the DRAM 120, the bus arbiter 130, and the first and second processing circuits 500 and 510 are manufactured on an LSI 110.
The CPU 160 controls the whole operation of the information processor. The DRAM 120 is a memory on which information associated with the operation of the information processor is written, which retains the information, and from which the information is read. When access to the DRAM 120 is requested by the CPU 160 and the first and second processing circuits 500 and 510, the bus arbiter 130 authorizes the access in order of descending priorities. The access port 140 comprises a register on which the information associated with the access request to the DRAM 120 output by the CPU 160 is written, and transmits the access request to the bus arbiter 130. The first and second processing circuits 500 and 510 are arbitrary processing circuits, and therefore the number of these circuits is not restricted to two.
FIG. 6 is a block diagram illustrating a structure of the access port 140. The access port 140 comprises a DRAM byte address specifying register 141, a DRAM word data reading/writing register 142, and an access mode specifying register 143. The access mode specifying register 143 comprises a DRAM address variability specifying bit 144 and a DRAM address increase/decrease specifying bit 145.
The DRAM byte address specifying register 141 is a register on which an address in the DRAM that the CPU 160 intends to access is written. The DRAM word data reading/writing register 142 retains the data of the address that has been written on the DRAM byte address specifying register 141 or data to be written at the address that has been written on the DRAM byte address specifying register 141. The access mode specifying register 143 specifies how to access the DRAM 120. The DRAM address variability specifying bit 144 specifies by 1 or 0 whether the address that has been written on the DRAM byte address specifying register 141 is to be consecutively varied or not. The DRAM address increase/decrease specifying bit 145 specifies by 1 or 0 whether the address that has been written on the DRAM byte address specifying register 141 is to be consecutively increased or decreased. address variability specifying bit 144 specifies by 1 or 0 whether the address which has been written on the DRAM byte address specifying register 141 is to be consecutively varied or not. The DRAM address increase/decrease specifying bit 145 specifies by 1 or 0 whether the address which has been written on the DRAM byte address specifying register 141 is to be consecutively increased or decreased.
Next, the access operation will be described with reference to FIGS. 5 and 6.
When the CPU 160 intends to read data at a predetermined address, for example an address of 0xc3x970500, 0 is written on the DRAM address variability specifying bit 144 and the address of 0xc3x970500 is written on the DRAM byte address specifying register 141. When the CPU 160 accesses contiguous addresses, for example addresses of 0xc3x970500 to 0xc3x970508, 1 is written on the DRAM address variability specifying bit 144, 1 is written on the DRAM address increase/decrease specifying bit 145, and the address of 0xc3x970500 is written on the DRAM byte address specifying register 141. In addition, when the CPU 160 accesses contiguous addresses in descending order, for example the addresses from 0xc3x970508 to 0xc3x970500, 1 is written on the DRAM address variability specifying bit 144, 0 is written on the DRAM address increase/decrease specifying bit 145, and the address of 0xc3x970508 is written on the DRAM byte address specifying register 141.
The CPU 160 outputs the access request to the bus arbiter 130 via the access port 140. When the access to the DRAM 120 is also requested by the first and second processing circuits 500 and 510, the bus arbiter 130 compares the request of the CPU 160 with the requests of the first and second processing circuits 500 and 510, and authorizes the access to the address for the request having the highest priority. For example, when the priority of the request by the CPU 160 is the highest, the bus arbiter 130 accesses the address requested by the CPU 160. The data at the accessed address are read into the DRAM word data reading/writing register 142. When the CPU 160 accesses the DRAM word data reading/writing register 142, it can read the data at the address for which the access request is made. At this time, when 0 has been written on the DRAM address variability bit 144, the reading is terminated. When 1 has been written on the DRAM address variability bit 144, the address which has been written on the DRAM byte address specifying register 141 is incremented or decremented in accordance with the specification of the DRAM address increase/decrease specifying bit 145. The data at the incremented or decremented address are read into the DRAM word data reading/writing register 142 via the bus arbiter 130.
When the CPU 160 intends to write data at a predetermined address in the DRAM 120, the CPU 160 writes the address on the DRAM byte address specifying register 141 and thereafter writes data to be written on the DRAM word data reading/writing register 142. When the CPU 160 accesses the requested address via the bus arbiter 130, the data which have been written on the DRAM word data reading/writing register 142 are written at the accessed address. When the CPU 160 intends to write data at contiguous addresses, the address in the DRAM byte address specifying register 141 is incremented or decremented using the above-mentioned DRAM address variability bit 144 and DRAM address increase/decrease specifying bit 145. Each time the address is incremented or decremented, the data which are to be written are written on the DRAM word data reading/writing register 142. Accordingly, the data can be consecutively written at the predetermined addresses.
Japanese Published Patent Application No.Hei.2-253440 discloses a time division multitask execution device which executes tasks which are written on plural register files with switching the tasks, using firmware.
When an access request to the DRAM 120 is output for the plural tasks of CPU multitask processing or interrupt processing while the CPU 160 accesses the DRAM 120 via the access port 140, the access, which has been executed until then, is interrupted. Then, information that is retained in the respective registers in the access port 140 is updated according to the tasks of the CPU multitask processing or interrupt processing.
However, in the above-mentioned system for accessing the DRAM 120 according to the prior art, even when the interrupted access is resumed, the address or data that has been updated in the middle may remain for some reason, whereby erroneous processing is executed.
For example, in order to execute a task of reading data at an address of 0xc3x970500 in the DRAM, the CPU 160 writes 0 on the DRAM address variability specifying bit 144 and writes 0xc3x970500 on the DRAM byte address specifying register 141. Here, when the interrupt processing is commanded immediately before the CPU 160 reads data of the DRAM word data reading/writing register 142, the CPU 160 interrupts the task, then writes the address that is requested by the interrupt processing, for example 0xc3x970800, on the DRAM byte address specifying register 141, and reads data of the DRAM word data reading/writing register 142. When the interrupt processing is completed, the CPU 160 executes the task which has been interrupted. However, the data at the address of 0xc3x970500 may be replaced with the data at the address of 0xc3x970800 which are read in the interrupt processing, for some reason.
As another example, in order to execute a task of writing desired data at contiguous addresses in the direction in which the address is increased +2 by +2 from the address of 0xc3x970500 in the DRAM 120 (0xc3x970500, 0xc3x970502, 0xc3x970504, . . . ), the CPU 160 writes 1 on the DRAM address variability specifying bit 144 and 1 on the DRAM address increase/decrease specifying bit 145, respectively, writes 0xc3x970500 on the DRAM byte address specifying register 141, and writes the desired data on the DRAM word data reading/writing register 142. When the interrupt processing is commanded after the data that have been written on the DRAM word data reading/writing register 142 are written at the addresses of 0xc3x970500 and 0xc3x970502, the CPU 160 interrupts the task, then writes the address of 0xc3x9700800 which is requested by the interrupt processing on the DRAM byte address specifying register 141, and reads the data at the address of 0xc3x970800 which are read into the DRAM word data reading/writing register 142. When the CPU 160 executes the task again, even when the task intends to write the data successively at the address of 0xc3x970504 in the DRAM, data may be written at the address of 0xc3x970802 for some reason.
In order to avoid the above-mentioned problem that an erroneous address or data may be processed when the interrupted task is resumed, there is the technique of taking measures against the problem on the firmware side controlling the CPU 160. For example, to execute a certain task, the CPU 160 writes 0 on the DRAM address variability specifying bit 144 and writes 0xc3x970500 on the DRAM byte address specifying register 141. When the interrupt processing is commanded immediately before the CPU 160 reads the data of the DRAM word data reading/writing register 142, the CPU 160 saves the respective information in the DRAM byte address specifying register 141, the DRAM word data reading/writing register 142 and the access mode specifying register 143 to a memory or the like under control of the CPU 160. Then, the CPU 160 writes the address which is requested by the interrupt processing, i.e., 0xc3x970800 on the DRAM byte address specifying register 141 and reads the data at 0xc3x970800 from the DRAM word data reading/writing register 142. When the CPU 160 resumes the interrupted task, the respective values of the registers, which have been saved to the memory under control of the CPU 160, are returned to the original registers.
As described above, when the task is interrupted by the plural tasks of the CPU multitask processing or interrupt processing, the information that has been written in the register is saved to the memory under control of the CPU 160. Then, when the interrupted task is resumed, the information which has been saved is returned to the register, whereby the address or data which is used in the tasks of the CPU multitask processing or interrupt processing does not remain in the register and the task can be executed normally. However, in this technique, the firmware controlling the CPU 160 has a complicated structure. In addition, when the tasks are switched frequently, the number of times that data in the register in the access port 140 are saved or saved data are returned is increased, whereby the CPU processing load is further increased.
In the time division multitask execution device disclosed in Japanese Published Patent Application No.Hei.2-253440, the execution of the tasks which have been written by the firmware on the respective register files is automatically switched and the states of use in the register files are managed directly by the CPU. Therefore, the load on the CPU is further increased.
The present invention is directed to solving the above-mentioned problems. It is an object of the present invention to provide an access controller that has a function of not accessing an erroneous address when a task which has been interrupted by the plural tasks of the CPU multitask processing or interrupt processing is resumed. More particularly, it is an object of the present invention to provide an access controller that suppresses the CPU processing load and does not require a complicated description of the firmware.
To attain the above-mentioned object, an access controller according to the present invention for relaying access from a CPU which can execute time division processing of plural tasks and interrupt processing to a predetermined memory, comprises: plural access ports in which information associated with the access from the CPU is stored for each access; and a management unit for managing use states of the plural access ports, and informing the CPU of the use states, and the CPU writes the information associated with the access on an unused one of the plural access ports on the basis of the use states provided by the management unit.
The access controller according to the present invention comprises the plural access ports. Therefore, even when the tasks are executed in the time division multiplexing, respective information of the tasks is written on different access ports, whereby an erroneous address is not accessed or erroneous data are not read or written. Further, the number of times that the tasks are switched is reduced as compared with the prior art having a saving function but having only one access port. Therefore, the tasks can be executed more efficiently, whereby the CPU processing load is reduced.
In addition, in the access controller according to the present invention, the management unit further comprises: a save area to which information stored in an arbitrary access port is saved so that information associated with an access request of another task or interrupt processing which is activated when the plural access ports are all in use is stored in the arbitrary access port; and save and return means for saving the information which has been written on the arbitrary access port to the save area, and returning the information which has been saved in the save area to the access port.
Therefore, the use states of the access ports and the saving or return of the information which has been written on the access port can be controlled by a small-scale circuit. Accordingly, the description of the firmware becomes simpler and the load on the CPU can be reduced. Further, the bank management unit comprises a save area. Therefore, even when the interrupt processing is requested when the access ports are all in use, data in one of the access ports which are in use is saved to the save area, whereby the interrupt processing can be executed.
Further, in the access controller according to the present invention, each of the access ports comprises: address specifying means for specifying an address in the memory which is to be accessed by the CPU; retaining means for temporarily retaining data which are read at the address specified by the address specifying means or data which are to be written at the address specified by the address specifying means; and address variability specifying means for specifying whether or not the address specified by the address specifying means is to be incremented or decremented.
In an access method according to the present invention for making access from a CPU which can execute time division processing of plural tasks and interrupt processing to a predetermined memory via an access controller having plural access ports and a management unit, the management unit recognizes use states of the plural access ports; the CPU stores information associated with the access in an arbitrary one of the access ports which is recognized by the management unit to be unused; the management unit records as the use state of the arbitrary access port in the management unit that the arbitrary access port is in use, when the information is stored in the arbitrary access port; the management unit makes access to the memory on the basis of the stored information; and the management unit records as the use state of the arbitrary access port in the management unit that the arbitrary access port is on standby, after the access is completed.
The access method according to the present invention uses the plural access ports. Therefore, even when the tasks are executed in the time division multiplexing, respective information of the tasks is written on different access ports, whereby an erroneous address is not accessed or erroneous data are not read or written. Further, the number of times that the tasks are switched is reduced as compared with the prior art having a save function but having only one access port. Therefore, the tasks can be executed more efficiently, whereby the CPU processing load can be reduced.
Further, in the access method of the present invention, the management unit saves information stored in an arbitrary one of the access ports to the management unit when recognizing that the plural access ports are all in use; the CPU stores information associated with access in the arbitrary access port; the management unit accesses the memory on the basis of the stored information; the management unit returns the information which has been saved to the management unit to the arbitrary access port after the access is completed; and the management unit resumes access on the basis of the returned information.
Therefore, the use states of the access port and the saving or return of the information which has been written on the access port can be controlled by a small-scale circuit. Therefore, the description of the firmware becomes simpler and the load on the CPU can be reduced. Further, the bank management unit comprises a save area. Therefore, even when the interrupt processing is requested when the access ports are all in use, data in one of the access ports which are in use are saved to the management unit, whereby the interrupt processing is executed.